2027 Graduate_Multimedia RTL Design Engineer

1. 01

   Develop high-performance VPU video codec IP blocks from

through hardware microarchitecture, design specification, RTL implementation, simulation, synthesis, integration, and release. 负责高性能VPU视频编解码IP模块的开发，涵盖需求分析、硬件微架构设计、设计规格编写、RTL实现、仿真、综合、集成和发布。

2. 02

   Collaborate with algorithm and architecture engineers to translate C/C++ reference models and codec tools into efficient hardware, balancing power, performance, area (PPA), latency, and memory bandwidth. 与算法和架构工程师协作，将C/C++参考模型和编解码工具转化为高效的硬件实现，并权衡功耗、性能、面积（PPA）、延迟和存储带宽。

3. 03

   Develop and optimize subsystem- and block-level Verilog/SystemVerilog RTL; participate in lint, CDC/RDC analysis, synthesis, timing analysis, and related issue closure. 开发并优化子系统级和模块级Verilog/SystemVerilog RTL；参与lint、CDC/RDC分析、综合、时序分析及相关问题闭环。

4. 04

   Perform block-level unit testing, self-checking, and debugging; cooperate with verification engineers on test planning, regression analysis, coverage closure, and root-cause investigation. 开展模块级单元测试、自验证和调试；与验证工程师协作完成测试规划、回归分析、覆盖率收敛和根因定位。

5. 05

   Support IP integration, FPGA and system validation, customer technical enablement, and root-cause analysis of codec hardware and system issues. 支持IP集成、FPGA和系统验证、客户技术支持，以及编解码硬件和系统问题的根因分析。

6. 06

   Prepare design and technical documentation, contribute to validation reports, and support invention disclosures or patent proposals when applicable. 编写设计及技术文档，参与验证报告整理，并根据需要支持发明提案或专利申请。 Job Requirements: 任职要求： Required Qualifications 基本要求

7. 01

   Master's or PhD degree in Electronic Engineering, Microelectronics, Computer Engineering, Computer Science, or a related field, graduating in 2027. 2027届硕士或博士毕业生，电子工程、微电子、计算机工程、计算机科学或相关专业。

8. 02

   Strong fundamentals in digital logic design, computer/SoC architecture, hardware microarchitecture, pipelining, memory systems, and timing concepts. 具备扎实的数字逻辑设计、计算机/SoC体系结构、硬件微架构、流水线、存储系统和时序基础。

9. 03

   Proficiency in Verilog or SystemVerilog, with practical experience in RTL design, simulation, and waveform debugging. 熟练掌握Verilog或SystemVerilog，并具有RTL设计、仿真和波形调试的实践经验。

10. 04

    Proficiency in at least one scripting or automation language, such as Python, Tcl, Perl, Shell/Bash, or Make; C/C++ knowledge is preferred. 熟练掌握Python、Tcl、Perl、Shell/Bash或Make等至少一种脚本或自动化语言；具备C/C++知识者优先。

11. 05

    Strong analytical and debugging skills, proactive collaboration with algorithm and verification engineers, and effective written and verbal communication in Mandarin and English. 具备良好的分析和调试能力，能够主动与算法及验证工程师协作，并具备有效的中英文书面和口头沟通能力。 Preferred Qualifications 加分项

12. 01

    Familiarity with ASIC/SoC/FPGA implementation flows and EDA tools for lint, CDC/RDC, simulation, synthesis, STA, or DFT; exposure to tools such as SpyGlass, VCS, Verdi, or Design Compiler is a plus. 熟悉ASIC/SoC/FPGA实现流程，以及lint、CDC/RDC、仿真、综合、STA或DFT相关EDA工具；接触过SpyGlass、VCS、Verdi或Design Compiler者优先。

13. 02

    Knowledge of one or more mainstream video coding standards, such as H.264/AVC, HEVC, AV1, VVC, or AVS. 了解H.264/AVC、HEVC、AV1、VVC或AVS等一种或多种主流视频编码标准。

14. 03

    Experience from internships, course projects, FPGA projects, IC design competitions, or open-source hardware contributions. 具有实习、课程项目、FPGA项目、集成电路设计竞赛或开源硬件贡献经历。 Job Location: Shanghai 工作地点： 上海