Layout Engineer

• Responsible for the development of physical IP layouts in advance CMOS and FinFET process.
• Perform physical verification(DRC/LVS/Antenna) for standard cell, memory, and IO, from bottom cells to top hierarchy.
• Capable of developing workflow automation for Memory compiler layout design.
• Undertake the assignments or in a team.
• Work closely with circuit design engineers to ensure highest quality physical IP layout.

Education and

• Bachelor degree in related fields such electrical engineering, computer science, physics and etc.
• Should have good understanding of basic CMOS, FinFET and SOI process and circuits.
• Experience or familiarly in various physical verification checks, like DRC, LVS, ERC, Antenna,Density, ESD, LUP, IREM, etc.
• Familiar with layout design and verification tools(virtuoso, Laker, Calibre).
• Familiar with process design principle and place and route effect.
• Familiar with script language, such as Perl, Python, TCL.
• Good communication skills, learning competency, self-motivated and team spirit.