CPU Design Verification Engineer

As an important member of our development team you'll predominantly be involved with employing constrained-random coverage-driven simulation techniques using SystemVerilog and UVM, both with hands-on project work and leading junior engineers.

You'll be responsible for:

• Ownership of a specific area of verification for a CPU, ranging from unit-level testbench development through to the overall verification strategy for the project.
• Full ownership of verification from initial investigation to closure.
• Architecting verification IP and full verification environments.
• Responsibility for producing test plans and verification strategies.
• Planning, tracking, and coordinating the tasks of you or your team to meet high quality goals at the planned time.
• Using a data driven approach to ensure a high-quality product.
• Evaluating and resolving causality of different issues throughout the verification process per project.

Job

• Experience of designing and implementing verification environments for complex RTL designs
• Well-versed in the use of hardware verification languages e.g. SystemVerilog and verification methodologies such as UVM
• Understanding of end-to-end verification processes, from test plan creation through to verification closure
• Ability to quickly understand and apply complex specification detail
• Good interpersonal skills and ability to work well as part of a team
• Ability to own all stages of a project to completion

Desirable skills and experience:

• Understanding of the fundamentals of computer architecture, with an emphasis on pipelining, exception handling, memory systems, system cache
• Working knowledge of scripting languages such as Python or Perl
• Software engineering skills including understanding of object-oriented programming, data structures, and algorithms.
• Experience with Functional Safety aspects of Design / Verification, knowledge of ISO 26262 is a plus
• Experience in Formal Verification testbenches is a plus

Additional responsibility for Senior and higher levels:

• Working as a senior member in a team: plan, track, and delivering tasks, mentoring other engineers to ensure on-time delivery against plans, requirements, or specs.

Additional essential qualification for Senior or higher levels:

• At least 8 years of experience in design verification, system validation, firmware programming, or digital design for comprehensive functional blocks with technologies such as computing, multimedia, or communication;
• Proven delivery record in CPU or similar level of model, analysis, design, implementation, verification, or validation for program flows, memory flows, I/O flows, asynchronous event flows, compute pipes, as well as system, processor, and pipe controls, by using leading edge design, verification, and implementation flows and methodologies.