NPU Design Verification Engineer

will be related, but not limited to: Ownership of a specific area of verification for Artificial Intelligence (AI) related IP Architect and implement verification environment for complex IPs using System Verilog, UVM, and/or C, System C etc. skills Work with design team and drive AI IP design into verification convergence, such as driving all types of coverage and complete corner case construction Develop scripting and infrastructure to support verification flow Work closely with software team in hardware-software codesign flow Learn emerging AI knowledge & technique and apply them over verification work Work under pressure to deliver IP to customer, track project verification status and resolve verification critical path Skills and Experience: Degree from EE. CS and good plus with

from circuit design 5 to 10 years design verification experience Deep understanding of CPU / DSP / AI-accelerator architecture & micro-architecture, memory / bus architecture and assembly language for ARM or other architecture Good understanding of AI operators such as convolution, pooling, etc. Deep understanding of design verification methodology Thorough knowledge of System Verilog and UVM Hands on experience on functional verification environment implementation, test case writing and RTL functional debug Experience in specification, creation, and debug of System Verilog/UVM constrained-random testbench Proficiency in scripting language such as Perl, TCL, Python Formal verification experience is a metric With excellent communication skill, teamwork and attention to details Our Culture We act with Belief—embracing uncertainty, owning challenges and driving solutions. With Solidarity, we align closely and back each other up. Staying Down-to-Earth, we drive efficiency, address customers’ real pain points and accelerate delivery. Fueled by Passion, we aim high, stay sharp, and never stop improving.