RTL Design Engineer for NPU

will be related, but not limited to:

• Architecture and Miro-architecture design for AI related IP products, writing detailed design specification for implementation
• Working closely with design team and verification team to complete quality design implementation
• As a design lead, providing guidance to junior engineers and driving the team to achieve design target
• Working closely with software team in hardware-software codesign flow, learning emerging AI knowledge & technique and apply them over innovation
• Analyzing and optimizing design over power / timing / area / memory bandwidth aspects
• Writing in-depth functional coverage and assertions, driving IP product verification convergence and product signoff
• Working under pressure to deliver IP to customer, track project status and resolve design critical path

Skills and Experience:

• Degree from EE. CS and good plus with

• from circuit design / computer science
• 5 to 10 years plus RTL design and micro-architecture design experienced 
• Deep understanding of modern computer architecture such as CPU / GPU/ DSP / AI-accelerator architecture, memory hierarchy / consistency and modern bus architecture such as AXI or ACE
• Interconnection development experience is a metric
• Good understanding of AI operators such as convolution, pooling etc.
• Deep understanding of design for low power, design for verification and design for reusage
• Thorough knowledge of Verilog / System Verilog
• System C and TLM experience will be preferable
• Formal verification experience will be a metric
• Line managing experience will be preferred
• On-track product delivery records and experiencing in design from specification, implementation to final signoff
• Proficiency in writing functional coverage and assertion
• With excellent communication skill, teamwork and attention to details