上海天数智芯半导体股份有限公司
ASIC Design Engineer – Memory Controller
岗位职责
1. Develop micro-architecture, write micro-architecture spec and other documents.
2. Write RTL code, meet the function target and have good performance/power/area efficiency.
3. Apply low power, DFT, DFD and other digital design techniques.
4. Work with DV team to improve test plan and debug failed tests.
5. Clean Lint, timing and other issues.
6. Participate in silicon debugging.
任职要求
1. Master in electrics or computer engineering.
2. At least 5 years working experience in ASIC logic design.
3. Familiar with DRAM structure and standards (DDR/LPDDR/GDDR/HBM), DFI interface protocol.
4. Experience with memory controller/ DRAM controller design.
5. Experience with memory controller performance debug and post silicon memory controller bring up.
6. Familiar with front-end EDA tools and flows.
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