Senior Memory Circuit Design Engineer

• Responsible for the development of physical IP (standard cell library, memory and IO) structure definition and circuit design on different process technology.
• Responsible for physical IP development flow and design methodology.
• Analyse and optimize physical IP timing, power and area.
• Guide layout engineer, assist in layout optimization based on post-simulation results.

Education and

• Master degree or above in related fields such electrical engineering, computer science, physics and etc.
• Good understanding semiconductor process/devices/physics, familiar with transistor lever circuit simulation and verification.
• Skillful in the use of EDA tools(virtuoso, spectre, hspice, HSIM, Finesim, StarRC etc.).
• Familiar with ASIC back-end flow(from RTL TO GDS): synthesis, STA, formal verification, CTS, place and route.
• Familiar with script language, such as Perl, Python, TCL.
• Good communication skills, learning competency, self-motivated and team spirit.