2027 Graduate_Standard Cell Library

1. 01

   Participate in the schematic design, physical layout design, and simulation verification of standard cell libraries. 参与标准单元库的电路设计（Schematic）、物理版图设计（Layout）及仿真验证工作；

2. 02

   Optimize the library's performance-power-area (PPA) metrics to meet design

across various process nodes. 优化标准单元库的性能、功耗与面积（PPA）指标，以满足不同工艺节点的设计要求；

3. 03

   Generate various library database views for standard cells, including GDS/CDL/LEF/NDM/LIB/DB/Verilog/ATPG/APLCHAR/PGV, etc. 生成标准单元库的多格式视图数据库，包括但不限于：GDS、CDL、LEF、NDM、LIB、DB、Verilog、ATPG、APLCHAR、PGV 等；

4. 04

   Library database views QA work to ensure database quality. 负责库视图数据库的 QA（质量保证）工作，确保交付的数据库质量；

5. 05

   Support standard library user guide documentation and maintenance. 支持标准单元库用户指南的编写与维护。

6. 06

   Proficiently use EDA tools (e.g., Cadence Virtuoso, Spectre, Innovus; Synopsys Primetime, ICC, Calibre) for library design, simulation, and verification. 熟练使用各类 EDA 工具（如 Cadence Virtuoso、Spectre、Innovus；Synopsys PrimeTime、ICC；以及 Calibre 等）进行库设计、仿真与验证；

7. 07

   Develop TCL/Perl/Python/Skill scripts to automate design flows and improve efficiency. 开发 TCL / Perl / Python / Skill 脚本，实现设计流程的自动化，提升工作效率。 Job Requirements: 任职要求:

8. 01

   Master's degree or above in Microelectronics, Integrated Circuit Design, Electronic Engineering, Computer Science, or related fields. 微电子、集成电路设计、电子工程、计算机科学或相关专业，硕士及以上学历；

9. 02

   Strong foundation in digital circuit design, familiarity with CMOS technology and semiconductor physics. 具备扎实的数字电路设计基础，熟悉 CMOS 工艺及半导体物理学；

10. 03

    Understanding of standard cell library design flows and basic concepts in timing analysis and power optimization. 了解标准单元库的设计流程，掌握时序分析与功耗优化的基本概念；

11. 04

    Familiarity with Linux operating systems; TCL/Perl/Python/Skill scripting skills are preferred. 熟悉 Linux 操作系统；具备 TCL / Perl / Python / Skill 等脚本编写能力者优先；

12. 05

    Prior experience with EDA tools (e.g., Cadence, Synopsys) for digital circuit design is a plus. 具备使用 EDA 工具（如 Cadence、Synopsys）进行数字电路设计经验者优先；

13. 06

    Experience with layout design tools (e.g., Virtuoso), circuit simulation (Spectre/HSPICE), or static timing analysis (e.g., PrimeTime) is a plus. 具备版图设计工具（如 Virtuoso）、电路仿真工具（如 Spectre/HSPICE）或静态时序分析工具（如 PrimeTime）实操经验者优先。 Job Location: Chengdu/Shanghai 工作地点: 成都/上海