2027 Graduate_Layout Engineer

1. 01

   Responsible for the development of physical IP layouts in advance CMOS and FinFET process; 负责先进 CMOS 及 FinFET 工艺下物理 IP 的版图开发工作；

2. 02

   Perform physical verification(DRC/LVS/Antenna) for standard cell, memory and IO, from bottom cells to top hierarchy. 执行标准单元库、存储器及 IO 的物理验证（DRC/LVS/天线效应检查），涵盖从底层单元到顶层层次结构的全流程；

3. 03

   Undertake the assignments independently or in a team. 能够独立或在团队中承担分配的任务；

4. 04

   Work closely with circuit design engineers to ensure highest quality physical IP layout. 与电路设计工程师紧密协作，确保交付最高质量的物理 IP 版图。 Job

任职要求

1. 01

   Bachelor degree in related fields such electrical engineering, computer science, physics and etc. 电子工程、计算机科学、物理等相关专业，本科及以上学历；

2. 02

   Should have good understanding of basic CMOS, FinFET and SOI process and circuits. 具备扎实的基础 CMOS、FinFET 及 SOI 工艺与电路知识；

3. 03

   Experience or familiarly in various physical verification checks, like DRC, LVS, ERC, Antenna, Density, ESD, LUP, IREM, etc.. 具备各类物理验证检查（如 DRC、LVS、ERC、天线效应、密度检查、ESD、LUP、IREM 等）的经验或熟悉度；

4. 04

   Familiar with layout design and verification tools(virtuoso, Laker, Calibre). 熟悉版图设计与验证工具（如 Virtuoso、Laker、Calibre）；

5. 05

   Familiar with process design principle and place and route effect. 熟悉工艺设计原理及布局布线（Place and Route）的物理效应；

6. 06

   Familiar with script language, such as Perl, Python, TCL. 熟悉脚本语言，如 Perl、Python、TCL 等；

7. 07

   Good communication skills, learning competency, self-motivated and team spirit. 具备良好的沟通能力、学习主动性、自我驱动力及团队合作精神。 Job Location: Chengdu/Shanghai 工作地点: 成都/上海