2027 Graduate_Circuit Design Engineer

1. 01

   Responsible for the development of physical IP (standard cell library, memory and IO) structure definition and circuit design on different process technology. 负责不同工艺节点下物理 IP（标准单元库、存储器及 IO）的架构定义与电路设计；

2. 02

   Responsible for physical IP development flow and design methodology. 负责物理 IP 的开发流程与整体设计方法论；

3. 03

   Analyze and optimize physical IP timing, power and area. 对物理 IP 的时序、功耗及面积（PPA）进行分析与优化；

4. 04

   Guide layout engineer, assist in layout optimization based on post-simulation results. 指导版图工程师，基于后仿真结果协助进行版图优化。 Job

任职要求

1. 01

   Master degree or above in related fields such electrical engineering, computer science, physics etc. 硕士及以上学历，电子工程、计算机科学、物理等相关专业背景；

2. 02

   Good understanding semiconductor process/devices/physics, familiar with transistor lever circuit simulation and verification. 具备扎实的半导体工艺/器件/物理基础，熟悉晶体管级电路仿真与验证；

3. 03

   Skillful in the use of EDA tools (virtuoso, spectre, hspice, HSIM, Finesim, StarRC etc.). 熟练使用各类 EDA 工具（如 Virtuoso, Spectre, HSPICE, HSIM, Finesim, StarRC 等）；

4. 04

   Familiar with ASIC back-end flow (from RTL TO GDS): synthesis, STA, formal verification, CTS, place and route. 熟悉 ASIC 后端设计全流程（从 RTL 到 GDS）：包括逻辑综合、静态时序分析（STA）、形式验证、时钟树综合（CTS）及布局布线（Place and Route）； 熟悉脚本语言，如 Perl、Python、TCL 等；

5. 05

   Familiar with script language, such as Perl, Python, TCL. 熟悉脚本语言，如 Perl、Python、TCL 等；

6. 06

   Good communication skills, learning competency, self-motivation and team spirit. 具备良好的沟通能力、学习主动性、自我驱动力及团队合作精神。 Job Location: Shanghai/Chengdu 工作地点: 上海/成都