Design Verification Engineer for Security

• You will contribute to the specification, microarchitecture of high performance, energy efficient IP solution. • Your responsibilities will be related, but not limited to, IP development applied to IoT, mobile, automotive, server areas etc. • You will be responsible for developing the formal property verification flow and the assume constraint for the DUT. • You will be responsible for Developing Test Bench with, but not limited to, System Verilog , UVM. • Develop and implement Verification Plan , test cases and functional coverage/assertion based on IP features, (e.g. methodologies/framework, bus functional models, regression tests). • Build Verification Environment using script Makefile/Perl/Python.

needed: • Education: Bachelors or Master’s degree in EE, CE or CS, or equivalent, with 3+ years of digital verification experience • Good experience on Building Test bench on IP or System level with System Verilog and UVM is required. • Very good understanding on Verilog, System Verilog, Verification Methodology. • Good communication skills, strong interpersonal skills and the flexibility. • Good understanding on AMBA. Experience in following will be a plus: • Good understanding of ARM based IP designs and system architecture. • Good experience on the formal property verification is preferred. • Rich background on UVM. • Experience on AMBA VIP. Personal Skills: • We are proud to have a set of behaviors that reflect our unique culture and guide our decisions, defining how we work together. • Strong desire to delivery result and win business. • Positive, “can do” attitude. • Self-motivated, dependable, and prompt. • Flexible, willing to adapt to changing responsibilities and assignments. • Good communicator, personable. • Capable of working as a team player. • Ethical, honest, and trustworthy. • Fluent in English. Job Location: Shanghai