Product Validation Engineer II

Test Strategy & Planning: Define comprehensive validation plans for new features, advanced nodes, and core engines of Innovus. Test Case Development: Create and maintain complex, realistic block-level and full-chip digital design test cases (RTL-to-GDSII). Flow Validation: Validate critical physical design stages including Synthesis, Placement, CTS, Routing, and post-Route Optimization. Automation & Scripting: Build, maintain, and optimize automated regression testing infrastructures. Bug Tracking & Triage: Identify, reproduce, isolate, and report software defects, collaborating closely with R&D teams to resolve them. Performance Benchmark: Analyze tool runtime, memory, and Quality of Results (QoR) including Timing (Setup/Hold), Power, and Area (PPA). Customer Scenario mimic: Replicate complex customer designs to ensure product reliability before commercial release. Required Skills &

Education: Bachelor’s or Master’s degree in Electronic Engineering, Microelectronics, Computer Engineering, or a related field. ASIC Design Knowledge: Deep understanding of the digital IC design flow, specifically Physical Design (Netlist-to-GDSII) and Static Timing Analysis (STA). EDA Tool Experience: Hands-on experience with Cadence Innovus (or other P&R tools). Scripting Skills: Proficiency in scripting languages, particularly Tcl (highly critical for EDA), as well as Python, Perl, or Shell scripting. Problem-Solving: Strong analytical skills to debug tool crashes, convergence issues, and timing/DRC violations. Communication: Excellent written and verbal communication skills in English to collaborate with global R&D and field application teams. Preferred Qualifications Experience with advanced technology nodes. Familiarity with sign-off tools such as Tempus (Timing) and power analysis tools such as Joules. Knowledge of software testing methodologies and AI skills.