Principal Application Engineer -Timing and power

To complete advanced SoC fullchip level STA and Timing ECO, especially have real large scale chip timing closure experience To complete advanced SoC power analysis for advanced process design, especially have complex low power project design and implementation experience To complete power analysis for both RTL level and gate level, also analysis and debug dynamic power toggle issues and find RTL design solutions To be familiar with low power design methodology, for example, multi-voltage, shut-down, DVFS/AVS etc. and be familiar with multi-voltage timing signoff To well analysis and optimize timing and congestion with SDC/STA skill, advanced nodes knowledge Use Tcl/Perl/Python to write scripts to improve work efficiency Position

Master with 7+ years working experience Ability to understand and articulate technical issues, (and knowledge of) design products and their applications. Requires working knowledge of one or more programming languages, and effective communication and soft skills. Be familiar with Joules/Genus/Innovus/Voltus/Tempus product is a plus. Good knowledge of verilog/spice/sdc/upf/lef/def/spef. Good communication in English and good work attitude. Be familiar with shell/Perl/Tcl etc. script language.