Senior Staff Engineer Radio Frequency Design (f/m/div)

Join our international RF and mixed-signal design team and drive the development of next-generation Frequency Synthesizers for cutting-edge semiconductor solutions. In this role, you will combine deep analog and RF expertise with digital-assisted design approaches, working closely with system architects, digital designers and validation experts from concept to silicon. Your role Key responsibilities in your new role PLL Concept & Architecture: Define and evaluate RF Digital PLL concepts (e.g., Fractional-N, ADPLL, Sub-sampling PLLs) and architectures tailored for high-frequency wireless applications Modeling & Noise Budgets: Develop high-level behavioral models (e.g., MATLAB, Simulink, Verilog-A) to analyze and optimize RF PLL loop dynamics, jitter, spurs, and stringent phase noise performance. Circuit Design & Implementation: Translate concepts into high-performance RF and mixed-signal circuits, focusing on critical blocks such as VCOs/DCOs, high-speed frequency dividers (prescalers), Phase-Frequency Detectors, and Charge Pumps, TDC, DTC Digitally-Assisted RF Calibration: Architect and verify digital calibration algorithms for PLL (e.g., spur mitigation, and mismatch compensation, TDC, DTC calibrations) to enhance RF performance System Partitioning: Partner closely with system architects, digital, and RF frontend teams to optimize mixed-signal and RF system partitioning for transceiver architectures Layout & Silicon Characterization: Guide layout engineers to preserve RF signal integrity, minimize parasitic effects, and ensure optimal isolation. Support laboratory validation teams during silicon characterization and debugging of the RF PLL

Qualifications and skills to help you succeed Education: A degree (Master/PhD preferred) in Electrical Engineering, Microelectronics, or a related field with a focus on RF/microwave design Experience: 5+ years of proven experience specifically focused on RF Digital PLL concept definition, architectural modeling, and circuit design Technical Expertise: Deep understanding of RF design principles, PLL loop theory, microwave engineering, noise analysis (Phase Noise, Jitter), and frequency synthesizer architectures for RF applications. Proficient in advanced CMOS and BiCMOS technologies Tools & Skills: Mastery of RF simulation environments (e.g., Cadence Spectre/SpectreRF, GoldenGate) and behavioral modeling tools (e.g., MATLAB, Simulink, Verilog-A) Leadership Skills: Proven technical leadership, mentoring skills, and project coordination capabilities Languages: Fluent in English (written and spoken). Knowledge of German is considered a plus We offer competitive salaries and additional benefits based on your performance, experience and qualification. The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group I ([外部招聘链接已隐藏] The monthly salary is paid 14 times p.a. We offer a higher compensation depending on your expertise and skills. #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon. Martin Gabernig [外部招聘链接已隐藏]