Digital Design Engineer(J11424)

Chip features specification and RTL design; Lint, CDC, UPF generation, Synthesis, verification, timing sign-off; FPGA emulation, lab validation and debugging.

MS in Electrical/Electronics Engineering; At least 3 years hands on experience with specification, micro-architecture, design, RTL coding, verification; Proficient in the use of industry standard languages and flows for RTL coding, synthesis, functional verification, timing analysis, power estimation and scripting; Nice to have a proven record of delivering successful ASICs from functional specification to the final product; One or more advantages as following are highly desirable: Hands on experience in WLAN MAC design and familiar with IEEE802.11 standard; A strong background in digital communication, signal processing and networking protocols; IC Design experiences in wireless communications; Experiences with ARM/RISC-V/DSP, NoC/AXI/AHB bus and External memory controller development; Familiar with IEEE802.3 standard is a plus; Excellent team and interpersonal skills; Clear written and verbal communication; Good communication skills in English; Desired to have cross-functional experience interacting with software, verification, and physical design teams.