SoC Verification Engineer/SoC验证工程师

同设计工程师配合，完成IP Level Feature点提取，完成IP Level UVM 验证环境搭建及验证； Cooperate with design engineers to complete IP Level Feature point extraction, complete IP Level UVM verification environment construction and verification.

提取SoC IP集成Feature，完成SoC IP 集成验证 ； Extract SoC IP integration Feature to complete SoC IP integration verification.

负责IP环境集成到SoC并在SoC验证； Responsible for IP environment integration into SoC and verification in SoC.

开发验证脚本（时钟，复位，pad等验证脚本）； Develop verification scripts (clock, reset, pad, etc.).

负责IP后仿验证工作。 Responsible for IP post verification.

集成电路，电气工程等专业硕士及以上学历； Master degree or above in IC, electrical engineering, etc.

有ASIC , SoC，IP验证环境搭建经验； Experience in building ASIC, SoC, IP verification environment.

对UVM验证方法学有深入了解； In-depth understanding of UVM verification methodology.

至少有3年的相关工作经验； At least 3 years of relevant work experience.

熟练掌握Verilog/System Verilog语言； Proficiency in Verilog / System Verilog language.

熟悉/ Python / Perl 等脚本语言； Familiar with scripting languages such as / Python / Perl.

标准的文档书写能力； Standard document writing skills.

熟练使用英文进行读写。 Proficient in reading and writing in English. 加分项： Additional desirable skills include:

有形式验证经验； Experiences in Formal verification.

有复杂IP验证环境开发经验； Experience in developing complex IP verification environments.

了解一些标准接口，如Ethernet，I2C，SPI，UART，CAN/CAN-FD，JTAG等； Knowledge about several standard interfaces, such as Ethernet, I2C, SPI, UART, CAN/CAN-FD, JTAG etc.

具有带新人经验。 Experience in leading newcomers.