台积电
IC Frontend design engineer
岗位职责
RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.
Design flow/methodology development and innovation for front-end design challenges.
Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.
任职要求
MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.
New graduate or 3+ years working experience.
Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.
Familiar with tcl/Perl/Python program.
招聘信息
招聘部门：NJDC
招聘人数：若干
岗位类别：IDL-NJDC
工作地点：南京市
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