台积电
【27届】IC Physical design engineer
岗位职责
Physical implementation of advanced technology chips.
Design methodology development and innovation for advanced technology challenges.
Be responsible for 22/16/12/10/7/5nm chip implementation for customer’s projects or internal system test chips.
Be responsible for advanced node PPA benchmark, and solution development.
EDA tool new features enablement.
Customer onsite/offsite supports will be required on demand.
任职要求
MS or above in EE, CS related fields. Experience in APR, physical verification, chip implementation, or CAD development is plus.
New graduate or 3+ years working experience in chip physical implementation.
Familiar with Synopsys/Cadence APR tools/flows.
Familiar with TCL/Perl/Python programming.
Experience with TSMC advanced technology is plus.
Proven record in production tape-outs is plus.
招聘信息
招聘部门:NJDC
招聘人数:2
岗位类别:IDL-NJDC
工作地点:南京市
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