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岗位聚合/Principal Product Engineer - DDR IP
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Cadence

Principal Product Engineer - DDR IP

⌖浦东新区、浦口区实习
66 天前更新2026/09/01
JOB#22327
RESPONSIBILITIES

岗位职责

will be a key member of technical staff in an organization responsible for activities including but not limited to pre-sales engagement with potential customers and post-sales technical support for integration, usage, and deployment of memory physical IP producs. This candidate will be the primary interface between customers, CDNS R&D and System Validation teams. Candidate should possess strong communication skills with ability to manage multiple priorities on a day-to-day basis. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear oral and written communication skills are must-have attributes in this role.


Job Description


 Primary Responsibilities:

○ Supporting pre-silicon integration, usage, and implementation of memory subsystem products

○ Helping with internal system integration and QA testing of memory subsystem products (Controller + PHY)

Analyzing and resolving complex subsystem application or implementation issues and providing professional guidance to customers

○ Supporting various memory PHY and controller SOC integration reviews and implementation reviews

○ Assisting customers with RTL and gate-level simulations to verify functionality

○ Assisting customers with timing closure and other aspects of physical integration

Participating in development and refinement of product documentation and checklists for customer

applications

○ Supporting post-silicon bringup and production test activities for customers as needed

Enhancing customer experience by providing prompt, thorough, and technically accurate responses to

customer questions

○ Leveraging AI-powered tools and assistants to enhance productivity, improve decision making, and maintain

high-quality customer deliverables.

○ Applying AI-powered analytics tools to extract insights, identify patterns, and generate actionable

recommendations from complex datasets


Position

REQUIREMENTS

任职要求

○ B.S Electrical/Computer Engineering (or similar degree) and 7+ years of overall experience -OR- M.S

Electrical/Computer Engineering (or similar degree) and 5+ years of overall experience

○ Experience working with DDR5/4/3, LPDDR5/4/3, HBM3, GDDR6 or similar IPs

○ Verilog RTL design and gate level verification experience

○ Synthesis and static timing analysis experience (physical implementation/verification experience is a plus)

○ Familiarity with industry standard DFT flows and test methodologies.

○ Familiarity with package and board design

○ Ability to read schematics and participate in SI/PI reviews for customer board/package implementation


Preferred Qualifications

○ Experience with Memory PHY and DSP based architecture

○ Experience with embedded microcontroller FW

○ Background with scripting and applying AI solutions to daily workflows

✓

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这个岗位已超出 7 天时效窗口(66 天前更新),可能已经停止招聘,建议先确认官方页面是否仍在招。

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岗位档案POSITION FILE
企业Cadence
地点浦东新区、浦口区
类型实习
发布日期2026/07/28
更新日期2026/09/01
申请截止尽快投递

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