UCIe前端数字设计工程师(J10891)

Develop design specification for block implementation of UCIe IPs;

WriteRTL code in Verilog HDL and Verification:

Write initialization and test&training Firmware for UCIe 3. Perform ASIC synthesis, netlist generation, block and chip level timing analysis:

Assist and interface for IP intergration;

Lab bring up and feature enablement on real silicon.

Years of industry experience in deep submicron ASIC design;

Expertise with HDL and design of high speed and highcomplexity digital logic required;

Experience with Low Power design (a plus);

Expertise of Computer Architecture and computer Arithmetic (a plus);

DDR-SDRAM/UCIe/PCIe/Serdes/Risc-V experience (a plus)；