平头哥-资深AI芯片互联架构师-上海

In this role, you will work with hardware and software engineering groups to define the next-generation inter-chip network architecture for high-performance AI chip and AI network. * Identifies the challenging problems, and evaluate various architectural solutions for the next-generation of network for AI chip and AI Super Pod. * Gets strong influences on future AI products by advanced architecture design as the excellent interface between software and hardware. * Leads architecture design of AI chip to chip interconnect subsystem, Scale-up Switch chip, C2C link, and etc. * Documents the high-level architecture specification. * Participation in defining the micro-architecture of key subsystem. * Strong technical leadership to achieve successful delivery of final silicon product. * Works closely with design, software, system, and verification team.

* Minimum Bachelor degree in Computer Science or Electronics Engineering; M.S. or Ph.D. degree is preferred. * Minimum of 12 years (for M.S.) 8 years (for Ph.D.) of experience on computer architecture or network chip design with proven silicon result. * Strong experience in at least one of the following areas and have experience of technical leadership of successful chip development from architecture design to final production is a must:

1. 01

   Server AI chip.

2. 02

   Smart NIC/RDMA/RoCE/DPU.

3. 03

   State-of-the-art Switch chip (25.6T and above). * Hand-on experience of high-speed interface, such as Die to Die, high speed long-reach SerDes, MAC/PCS, FEC is a plus. * Hand-on experience of interconnects in AI domain is a big plus. * Strong knowledge of AI infrastructure and AI network including Scale-up/Scale-out network, and knowledge of LLM inference and training is a big plus. * Good verbal and written skill for communication.