IC版图设计工程师

Core Layout Design: Lead the physical layout design of foundation IPs, including Standard Cell, I/O, SRAM, NVM, Analog, Mixed-Signal, Testline, and Testchip, while driving the successful release of related library formats.

PPA Optimization: Drive DTCO (Design Technology Co-Optimization) solutions to achieve optimal PPA (Performance, Power, and Area) targets across advanced process nodes.

Cross-Functional Collaboration: Partner closely with circuit design engineers and cross-functional teams to co-design, optimize, and maintain robust, high-quality IP libraries.

SOP & Compliance: Strictly adhere to standard operating procedures (SOPs) and design rules across various process nodes to ensure first-time-right silicon.

AI & Automation Integration: Develop and deploy automation scripts and AI-driven methodologies to enhance QA verification checks and boost layout productivity.

Project & Quality Management: Take ownership of project deliverables, ensuring top-tier quality and strict adherence to schedules, while proactively upgrading technical skills and project management efficiency.

BCH and above degree in EE related field.

Expertise on semiconductor, device, circuit and familiar with EDA tools e.g. Cadence,Synopsys, Siemens will be a plus.

Scripting skill such as python/TCL/Skill is a plus.

Open to highly self-motivated candidates with solid design backgrounds; intensive custom layout experience is preferred but not required.