台积电
IC版图设计工程师
RESPONSIBILITIES
岗位职责
Full layout design for std cell/IO/SRAM IPs in advanced node
Work on the physical verification(DRC/LVS/Antenna ...)
Work on test chip layout design and verification
Close cooperation with designers on PPA optimization
REQUIREMENTS
任职要求
At least Master Degree of Microelectronics or Physics.
Excellent graduate or at least 1 years' related working experience
Familiar with layout design and verification tools(Virtuoso,Laker,Calibre)
Familiar with design rule and layout effect in advanced process.
Excellent skills of communication and teamwork are also expected.
Programming experience（perl/tcl skill） will be a plus.
Experience in advanced process (n16 and beyond) will be a plus.
信息来自企业官方招聘渠道
OfferSeek 对公开岗位信息进行聚合、去重和结构化整理，最终申请以企业官方页面为准。